This invention concerns a digital signal processor in which a mathematical operation is carried out between non-delayed and delayed data.
Such a processor may perform an auto or cross correlation function, or a structure function calculation.
In a typical digital correlator an input signal is divided into successive sample intervals. Digital numbers representative of the signal during each sample interval are clocked serially through the correlator for correlation. A series of digital numbers is clocked along an M-stage shift register to form a delayed signal. A non-delayed series of digital numbers is applied to one input of M different multipliers. The other input of these multipliers is taken from successive stages of the shift register. Each multiplier thus operates on a different delay. The output of each multiplier is accumulated in one of M different counters providing M different channels. At the end of an experimental run the collective content of the counters represents the correlation function of the input signal or signals. This correlator may be termed a linear correlator because the delay between successive channels increases linearly.
An alternative type of digital signal processor measures the "structure function" of the input signal which for long experiments has an equivalent form to the correlation function. To measure this alternative function a "structurator" is required which operates exactly as a correlator described above except that the multiply circuits are replaced by circuits which subtract their two inputs and then square the results.
The correlator may perform an auto correlation or a cross correlation on data. For an auto correlation the input signal is replicated into two identical signals; one signal is delayed and multiplied by the other non-delayed signal. For a cross correlator a first signal is delayed and multiplied with a second, but non delayed, signal.
Digital signal processing enables highly accurate mathematical operations to be carried out on signals. Due to recent advances in logic speed complicated processing can be carried out in real time. Also advances in the statistical theories of some events have simplified the processing of some functions. One example of this is in laser light scattering experiments, particularly in weak scattering events.
Detailed investigation into the properties of light scattering led to the development of a single clipped digital correlator described in U.K. Patent Specification No. 1,290,336. This correlator allowed the processing of signals representing the arrival of single photons on a sensitive detector. From this a whole range of work has been made possible, for example, laser light scattering where the light scattered by a suspension of particles in a liquid can be processed to give particle diffusion co-efficients.
In the above linear digital correlator a correlation function is accumulated from information obtained in successive sample interval channels. Increasing the number of sample channels allows further information to be obtained but results in increased equipment costs.
One solution to the problem of collecting information from many sample intervals is described in G.B. No. 2,115,192 A and its U.S. equivalent U.S. Pat. No. 4,593,378. In this specification the time delay between each channel is geometrically increased. Thus for example using 26 channels with a .sqroot.2 progression between channels information can be obtained from the equivalent of a delay interval of 8192 in a linear correlator e.g. G.B. No. 1,290,336 and its U.S. equivalent U.S. Pat. No. 3,842,252. The correlator of G.B. No. 2,115,192 A relies on correlating a signal, at geometrically increasing delays, to obtain the maximum information for a given number of channels. However information is still available from the non-correlated delays. Such uncollected information becomes more important at low counting rates. G.B. No. 2,115,192 A also applies to the principle of increasing delays to a measurement of the structure function.
The present invention extends the data collected from a correlator or structurator such as taught by G.B. No. 2,115,192 A, without the huge increases in equipment channels that would be involved if the linear correlator of G.B. No. 1,290,336 were merely extended.
According to this invention in a multi-channel correlator or structurator both the time delay between channels and sampling times in successive channels are progressively increased.
According to this invention a multi-channel digital signal processor has:
a device for receiving series of digital numbers in successive sample time intervals (T); PA1 an accumulator for counting the total number of digital signals received; PA1 a plurality of channels each having PA1 a device for progressively increasing the sample time interval (T.sub.s) in successive channels; and PA1 a device for increasing the delay (.tau.) in successive channels.
a series of delays along which a series of digital numbers is transferred to provide a delayed signal, PA2 an arithmetic section for receiving at one input a digital signal and at another input the delayed signal, and PA2 an accumulator for receiving the output of the arithmetic section;
The arithmetic section may be a multiplier, in which case the processor is a correlator. Alternatively the arithmetic section may be a difference squarer circuit, in which case the processor is a structurator.
The delayed signal in each channel may be obtained by clocking a digital signal along a multistage multibit shift register.
The means for progressively increasing the channel sample time (T.sub.s) may be frequency dividers set to divide the sample time T by set amounts to clock the delayed signal. These frequency dividers may have fixed values or be changeable to suit differing experiments.
The increase in T.sub.s, between channels m and m-1 may be a constant multiplicative factor, i.e. EQU T.sub.s.sup.(m) =.alpha.T.sub.s.sup.(m-1) ( 1) EQU so that EQU T.sub.s.sup.(m) =.alpha..sup.M-1 T.sub.s.sup.(1) ( 2)
.alpha. may be an integer or may take a non-integral value with .alpha..sup.m-1 rounded to the nearest integer. The delay time .tau. may be a fixed or variable multiple of T.sub.s e.g. EQU .tau..sup.(m) =.beta.T.sub.s.sup.(m) ( 3)
where .beta. is an integer.